/*******************************************************************************
* @copyright: Shenzhen Hangshun Chip Technology R&D Co., Ltd
* @filename:  hk32c030xx_rcc.c
* @brief:     RCC initialization and configuration
* @author:    AE Team
* @version:   V1.0.0/2023-06-22
*             1.Initial version
* @log:
*******************************************************************************/


/* Includes ------------------------------------------------------------------*/
#include "hk32c030xx_rcc.h"


/** @addtogroup HK32C030xx_StdPeriph_Driver
  * @{
  */

/** @defgroup RCC RCC
  * @brief RCC driver modules
  * @{
  @verbatim
        ===============================================================================
                        ##### RCC specific features #####
        ===============================================================================
        [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
         all peripherals are off except internal SRAM, Flash and SWD.
            (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
             all peripherals mapped on these busses are running at HSI speed.
            (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
            (#) All GPIOs are in input floating state, except the SWD pins which
             are assigned to be used for debug purpose.
        [..] Once the device started from reset, the user application has to:
            (#) Configure the clock source to be used to drive the System clock
             (if the application needs higher frequency/performance)
            (#) Configure the System clock frequency and Flash settings
            (#) Configure the AHB and APB busses prescalers
            (#) Enable the clock for the peripheral(s) to be used
            (#) Configure the clock source(s) for peripherals which clocks are not
             derived from the System clock (ADC, I2C, UART, RTC and IWDG)

  *  @endverbatim
  */

/** @defgroup RCC_Private_Macro_Define RCC_Private_Macro_Define
  * @brief   RCC Macro Define table
  * @{
  */

/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/


/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/

/* ---------------------- RCC registers mask -------------------------------- */
/* RCC Flag Mask */
#define FLAG_MASK                 ((uint8_t)0x1F)

/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};

/**
  * @}
  */

/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
 *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions
 *
@verbatim
 ===============================================================================
 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
 ===============================================================================
    [..] This section provides functions allowing to configure the internal/external clocks,
         PLL, CSS and MCO.
         (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
             or through the PLL as System clock source.
             The HSI clock can be used also to clock the UART, I2C and CEC peripherals.
         (#) HSI16 (high-speed internal for ADC), 16 MHz factory-trimmed RC used to clock
             the ADC peripheral.
         (#) HSI64
         (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
             clock source.
         (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
             through the PLL as System clock source. Can be used also as RTC clock source.
         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
             LSE can be used also to clock the UART peripherals.
         (#) PLL (clocked by HSI or HSE), for System clock.
         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
             (HSE used directly or through PLL as System clock source), the System clock
             is automatically switched to HSI and an interrupt is generated if enabled.
             The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
             exception vector.
         (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI16, LSI,
             HSE, LSE or PLL (divided by 2) clock on PA8 pin.

@endverbatim
  * @{
  */

/**
  * @brief  Resets the RCC clock configuration to the default reset state.
  * @note   The default reset state of the clock configuration is given below:
  * @note   HSI ON and used as system clock source
  * @note   HSI16, HSE and PLL OFF
  * @note   AHB, APB prescaler set to 1.
  * @note   CSS and MCO OFF
  * @note   All interrupts disabled
  * @note   However, this function doesn't modify the configuration of the
  * @note   Peripheral clocks
  * @note   LSI, LSE and RTC clocks
  * @retval None
  */
void RCC_DeInit(void)
{
    /* Set HSION bit */
    RCC->CR |= (uint32_t)0x00000001;
    /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], MCO[3:0], MCOPRE[2:0] and PLLNODIV bits */
    RCC->CFGR &= (uint32_t)0x00FFF80C;
    /* Reset HSEON, HSEBYP, CSSON and PLLON bits */
    RCC->CR &= (uint32_t)0xFEF2FFFF;
    /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
    RCC->CFGR &= (uint32_t)0xFFC0FFFF;
    /* Reset PREDIV[3:0] bits */
    RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
    /*Reset UART5SW[1:0], UART4SW[1:0] and UART3SW[1:0] Bits*/
    RCC->CFGR3 &= (uint32_t)0xFF03FFFF;
    /* Reset UART1SW[1:0], I2C1SW bits ,UART2SW[1:0]*/
    RCC->CFGR3 &= (uint32_t)0xFFFCFFEC;
    /* Reset HSI16 bit */
    RCC->CR2 &= (uint32_t)0xFFFFFFFE;
    /* Reset HSI64 bit */
    RCC->CFGR4 &= (uint32_t)0xFFFEFFFF;
    /*Reset I2C2CLK_SEL[1:0], I2C1CLK_SEL, FLITFCLK_PRE[3:0], FLITFCLK_SEL[1:0]*/
    RCC->CFGR4 &= (uint32_t)0xF3FF01FF;
    /*Reset PLLMULH[2:0], LPTIMSW[1:0], LPUARTSW[1:0], USBDIV[2:0], USBIFDIV[1:0] and WKRSTBUSCK bits*/
    RCC->CFGR4 &= (uint32_t)0xF8F007FE;
    /* Disable all interrupts */
    RCC->CIR = 0x00000000;
}

/**
  * @brief  Configures the External High Speed oscillator (HSE).
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
  *         software should wait on HSERDY flag to be set indicating that HSE clock
  *         is stable and can be used to clock the PLL and/or system clock.
  * @note   HSE state can not be changed if it is used directly or through the
  *         PLL as system clock. In this case, you have to select another source
  *         of the system clock then change the HSE state (ex. disable it).
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
  * @note   This function resets the CSSON bit, so if the Clock security system(CSS)
  *         was previously enabled you have to enable it again after calling this
  *         function.
  * @param  RCC_HSE: specifies the new state of the HSE.
  *         This parameter can be one of the following values:
  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
  *                 6 HSE oscillator clock cycles.
  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_HSEConfig(uint8_t RCC_HSE)
{
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_HSE));
    /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
    RCC->CR &= ~RCC_CR_HSEON;
    RCC->CR &= ~RCC_CR_HSEBYP;

    /* Set the new HSE configuration -------------------------------------------*/
    if (RCC_HSE == RCC_HSE_OFF)
    {
        RCC->CR &= ~RCC_CR_HSEON;
    }
    else if (RCC_HSE == RCC_HSE_ON)
    {
        RCC->CR |= RCC_CR_HSEON;
    }
    else
    {
        RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
    }
}

/**
  * @brief  Waits for HSE start-up.
  * @note   This function waits on HSERDY flag to be set and return SUCCESS if
  *         this flag is set, otherwise returns ERROR if the timeout is reached
  *         and this flag is not set. The timeout value is defined by the constant
  *         HSE_STARTUP_TIMEOUT in hk32c030xx_conf.h file. You can tailor it depending
  *         on the HSE crystal used in your application.
  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
  * @retval An ErrorStatus enumeration value:
  *         - SUCCESS: HSE oscillator is stable and ready to use
  *         - ERROR: HSE oscillator not yet ready
  */
ErrorStatus RCC_WaitForHSEStartUp(void)
{
    __IO uint32_t StartUpCounter = 0;
    ErrorStatus status = ERROR;
    FlagStatus HSEStatus = RESET;

    /* Wait till HSE is ready and if timeout is reached exit */
    do
    {
        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
        StartUpCounter++;
    } while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));

    if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
    {
        status = SUCCESS;
    }
    else
    {
        status = ERROR;
    }

    return (status);
}


/**
  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
  * @note   After enabling the HSI, the application software should wait on
  *         HSIRDY flag to be set indicating that HSI clock is stable and can
  *         be used to clock the PLL and/or system clock.
  * @note   HSI can not be stopped if it is used directly or through the PLL
  *         as system clock. In this case, you have to select another source
  *         of the system clock then stop the HSI.
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
  * @param  NewState: new state of the HSI.
  *         This parameter can be: ENABLE or DISABLE.
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_HSICmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CR |= RCC_CR_HSION;
    }
    else
    {
        RCC->CR &= ~RCC_CR_HSION;
    }
}


/**
  * @brief  Enables or disables the Internal High Speed oscillator for ADC (HSI16).
  * @note   After enabling the HSI16, the application software should wait on
  *         HSIRDY flag to be set indicating that HSI clock is stable and can
  *         be used to clock the ADC.
  * @note   The HSI16 is stopped by hardware when entering STOP and STANDBY modes.
  * @param  NewState: new state of the HSI16.
  *         This parameter can be: ENABLE or DISABLE.
  * @note   When the HSI16 is stopped, HSI16RDY flag goes low after 6 HSI16 oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_HSI16Cmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CR2 |= RCC_CR2_HSI16ON;
    }
    else
    {
        RCC->CR2 &= ~RCC_CR2_HSI16ON;
    }
}

/**
  * @brief  Enables or disables the Internal High Speed oscillator(HSI64).
  * @note   After enabling the HSI64, the application software should wait on
  *         HSIRDY flag to be set indicating that HSI clock is stable.
  * @note   The HSI64 is stopped by hardware when entering STOP and STANDBY modes.
  * @param  NewState: new state of the HSI64.
  *         This parameter can be: ENABLE or DISABLE.
  * @note   When the HSI64 is stopped, HSI64RDY flag HSI64 oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_HSI64Cmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CFGR4 |= RCC_CFGR4_HSI64ON;
    }
    else
    {
        RCC->CFGR4 &= ~RCC_CFGR4_HSI64ON;
    }
}

/**
  * @brief  Configures the External Low Speed oscillator (LSE).
  * @note   As the LSE is in the Backup domain and write access is denied to this
  *         domain after reset, you have to enable write access using
  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
  *         (to be done once after reset).
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
  *         software should wait on LSERDY flag to be set indicating that LSE clock
  *         is stable and can be used to clock the RTC.
  * @param  RCC_LSE: specifies the new state of the LSE.
  *         This parameter can be one of the following values:
  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
  *                 6 LSE oscillator clock cycles.
  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_LSEConfig(uint32_t RCC_LSE)
{
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_LSE));
    /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
    /* Reset LSEON bit */
    RCC->BDCR &= ~(RCC_BDCR_LSEON);
    /* Reset LSEBYP bit */
    RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
    /* Configure LSE */
    RCC->BDCR |= RCC_LSE;
}

/**
  * @brief  Configures the External Low Speed oscillator (LSE) drive capability.
  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
  *         This parameter can be one of the following values:
  *            @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
  *            @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
  *            @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
  *            @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
  * @retval None
  */
void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
{
    /* Check the parameters */
    assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
    /* Clear LSEDRV[1:0] bits */
    RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
    /* Set the LSE Drive */
    RCC->BDCR |= RCC_LSEDrive;
}

/**
  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
  * @note   After enabling the LSI, the application software should wait on
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
  *         be used to clock the IWDG and/or the RTC.
  * @note   LSI can not be disabled if the IWDG is running.
  * @param  NewState: new state of the LSI.
  *         This parameter can be: ENABLE or DISABLE.
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  *         clock cycles.
  * @retval None
  */
void RCC_LSICmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CSR |= RCC_CSR_LSION;
    }
    else
    {
        RCC->CSR &= ~RCC_CSR_LSION;
    }
}

/**
  * @brief  Enables or disables the PLL.
  * @note   After enabling the PLL, the application software should wait on
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
  *         be used as system clock source.
  * @note   The PLL can not be disabled if it is used as system clock source
  * @note   The PLL is disabled by hardware when entering STOP and STANDBY modes.
  * @param  NewState: new state of the PLL.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_PLLCmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CR |= RCC_CR_PLLON;
    }
    else
    {
        RCC->CR &= ~RCC_CR_PLLON;
    }
}


/**
  * @brief  Configures the PLL clock source and multiplication factor.
  * @note   This function must be used only when the PLL is disabled.
  * @param  RCC_PLLSource: specifies the PLL entry clock source.
  *         This parameter can be one of the following values:
  *            @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source div 2
  *            @arg RCC_PLLSource_HSE:  HSE oscillator clock selected as PLL clock source,
  *            @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry     *
  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
  *         This parameter can be RCC_PLLMul_x where x:[2,16]
  * @retval None
  */
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{
    uint32_t tmp = 0;
    uint32_t tmpreg = 0;
    /* Check the parameters */
    assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
    assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
    /* Clear PLL Source [16] and Multiplier [21:18] bits */
    RCC->CFGR &= ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC);
    tmp = RCC_PLLSource >> 4;

    if (tmp == 0)
    {
        /* Set the PLL Source and Multiplier */
        RCC->CFGR |= (uint32_t)((RCC_PLLSource << RCC_CFGR_PLLSRC_Pos) | RCC_PLLMul);
    }
    else
    {
        /* Clear PPSS bits */
        RCC->CFGR4 &= ~RCC_CFGR4_PPSS;
        /* The PLL clock source is determined by the PPSS bits in the CFGR4 register */
        tmpreg = (uint32_t)(RCC_PLLSource & 0x0F) << RCC_CFGR4_PPSS_Pos;
        RCC->CFGR4 |= tmpreg;
        RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_PLLMul);
    }
}

/**
  * @brief  Configures the PREDIV division factor.
  * @note   This function must be used only when the PLL is disabled.
  * @param  RCC_PREDIV_Div: specifies the PREDIV1 clock division factor.
  *         This parameter can be RCC_PREDIV1_Divx where x:[1,16]
  * @retval None
  */
void RCC_PLLPREDIVConfig(uint32_t RCC_PREDIV_Div)
{
    uint32_t tmpreg = 0;
    /* Check the parameters */
    assert_param(IS_RCC_PREDIV(RCC_PREDIV_Div));
    tmpreg = RCC->CFGR2;
    /* Clear PREDIV1[3:0] bits */
    tmpreg &= ~(RCC_CFGR2_PREDIV);
    /* Set the PREDIV1 division factor */
    tmpreg |= RCC_PREDIV_Div;
    /* Store the new value */
    RCC->CFGR2 = tmpreg;
}

/**
  * @brief  Enables or disables the Clock Security System.
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
  *         is automatically disabled and an interrupt is generated to inform the
  *         software about the failure (Clock Security System Interrupt, CSSI),
  *         allowing the MCU to perform rescue operations. The CSSI is linked to
  *         the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
  * @param  NewState: new state of the Clock Security System.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->CR |= RCC_CR_CSSON;
    }
    else
    {
        RCC->CR &= ~RCC_CR_CSSON;
    }
}

/**
  * @brief  Adjusts the CSS counter threshold control.
  * @note   After the CSS function is enabled, RCC uses the HSI clock to sample the HSE frequency division waveform.
  *         If the FREQUENCY of HSE input is very low, CSS outages can be triggered even when the HSE is still working.
  *         You can adjust the value through CSS_THRESHOLD[6:0] to avoid. When different thresholds are configured,
  *         the lowest HSE frequency determined by the CSS is about 4M/ CSS_THRESHOLD[6:0].
  * @param  CSS_THRESHOLD_Value: specifies the CSS counter threshold control value.
  *         This parameter must be a number between 0 and 0x3F.
  * @retval None
  */
void RCC_CSSThresholdConfig(uint8_t CSS_THRESHOLD_Value)
{
    uint32_t tmpreg = 0;
    assert_param(IS_CSS_THRESHOLD_Value(CSS_THRESHOLD_Value));
    tmpreg = RCC->HSECTL ;
    tmpreg &= ~RCC_HSECTL_CSS_THRESHOLD;
    tmpreg |= (uint32_t)CSS_THRESHOLD_Value << 25 ;
    RCC->HSECTL = tmpreg;
}

/**
  * @brief  Selects the clock source to output on MCO pin (PA8) and the corresponding
  *         prescsaler.
  * @note   PA8 should be configured in alternate function mode.
  * @param  RCC_MCOSource: specifies the clock source to output.
  *         This parameter can be one of the following values:
  *            @arg RCC_MCOSource_NoClock: No clock selected.
  *            @arg RCC_MCOSource_HSI16: HSI16 oscillator clock selected.
  *            @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
  *            @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
  *            @arg RCC_MCOSource_SYSCLK: System clock selected.
  *            @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
  *            @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
  *            @arg RCC_MCOSource_PLLCLK_Div2: PLL/2 clock selected.
  * @param  RCC_MCOPrescaler: specifies the prescaler on MCO pin.
  *         This parameter can be one of the following values:
  *            @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
  *            @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
  *            @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
  *            @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
  *            @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
  *            @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
  *            @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
  *            @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
  * @retval None
  */
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
{
    uint32_t tmpreg = 0;
    /* Check the parameters */
    assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
    assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
    /* Get CFGR value */
    tmpreg = RCC->CFGR;
    /* Clear MCOPRE[2:0] bits */
    tmpreg &= ~(RCC_CFGR_MCOPRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
    /* Set the RCC_MCOSource and RCC_MCOPrescaler */
    tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource << RCC_CFGR_MCO_Pos));
    /* Store the new value */
    RCC->CFGR = tmpreg;
}


/**
  * @}
  */

/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
 *  @brief   System, AHB and APB busses clocks configuration functions
 *
 @verbatim
 ===============================================================================
     ##### System, AHB and APB busses clocks configuration functions #####
 ===============================================================================

    [..] This section provide functions allowing to configure the System, AHB and
         APB busses clocks.
         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
             HSE and PLL.
             The AHB clock (HCLK) is derived from System clock through configurable prescaler
             and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
             and APB (PCLK) clocks are derived from AHB clock through
             configurable prescalers and used to clock the peripherals mapped on these busses.
             You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.

         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
             (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
             (+@) The UART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
             (+@) The RTC clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
                  divided by a programmable prescaler).
                  The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
                  clock frequency.
             (+@) IWDG clock which is always the LSI clock.

         (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 72 MHz.
             Depending on the maximum frequency, the FLASH wait states (WS) should be
             adapted accordingly:
        +--------------------------------------------- +
        |  Wait states  |   HCLK clock frequency (MHz) |
        |---------------|------------------------------|
        |0WS(1CPU cycle)|       0 < HCLK <= 24         |
        |---------------|------------------------------|
        |1WS(2CPU cycle)|       24 < HCLK <= 48        |
        |---------------|------------------------------|
        |2WS(3CPU cycle)|       48 < HCLK <= 72        |
        +----------------------------------------------+

         (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
             prefetch is disabled.

    [..] It is recommended to use the following software sequences to tune the number
         of wait states needed to access the Flash memory with the CPU frequency (HCLK).
         (+) Increasing the CPU frequency
         (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
              function
         (++) Check that Flash Prefetch buffer activation is taken into account by
              reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
         (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
         (++) Check that the new CPU clock source is taken into account by reading
              the clock source status, using "RCC_GetSYSCLKSource()" function
         (+) Decreasing the CPU frequency
         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
         (++) Check that the new CPU clock source is taken into account by reading
              the clock source status, using "RCC_GetSYSCLKSource()" function
         (++) Program the new number of WS, using "FLASH_SetLatency()" function
         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
         (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
              function
         (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
              using the FLASH_GetPrefetchBufferStatus() function.

@endverbatim
  * @{
  */

/**
  * @brief  Configures the system clock (SYSCLK).
  * @note   The HSI is used (enabled by hardware) as system clock source after
  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
  *         of failure of the HSE used directly or indirectly as system clock
  *         (if the Clock Security System CSS is enabled).
  * @note   A switch from one clock source to another occurs only if the target
  *         clock source is ready (clock stable after startup delay or PLL locked).
  *         If a clock source which is not yet ready is selected, the switch will
  *         occur when the clock source will be ready.
  *         You can use RCC_GetSYSCLKSource() function to know which clock is
  *         currently used as system clock source.
  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source
  *         This parameter can be one of the following values:
  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
  *            @arg RCC_SYSCLKSource_LSE:    LSE selected as system clock source
  *            @arg RCC_SYSCLKSource_LSI:    LSI selected as system clock source
  *            @arg RCC_SYSCLKSource_HSI64:  HSI64 selected as system clock source
  *            @arg RCC_SYSCLKSource_HSI16:  HSI16 selected as system clock source
  *            @arg RCC_SYSCLKSource_EXTCLK: EXTCLK selected as system clock source
  * @retval None
  */
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{
    uint32_t tmpreg = 0, tmp = 0;
    /* Check the parameters */
    assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
    /* Clear ESSS bits */
    RCC->CFGR4 &= ~RCC_CFGR4_ESSS;
    tmp = RCC_SYSCLKSource >> 4;

    if (tmp == 0)
    {
        tmpreg = RCC->CFGR;
        /* Clear SW[1:0] bits */
        tmpreg &= ~RCC_CFGR_SW;
        /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
        tmpreg |= RCC_SYSCLKSource;
        /* Store the new value */
        RCC->CFGR = tmpreg;
    }
    else
    {
        tmpreg = RCC->CFGR4;
        /* Clear SW[1:0] bits */
        tmpreg &= ~RCC_CFGR4_ESW;
        /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
        tmpreg |= (RCC_SYSCLKSource & 0x7) | RCC_CFGR4_ESSS;
        /* Store the new value */
        RCC->CFGR4 = tmpreg;
    }
}

/**
  * @brief  Returns the clock source used as system clock.
  * @retval The clock source used as system clock. The returned value can be one
  *         of the following values:
  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
  *            @arg RCC_SYSCLKSource_LSE:    LSE selected as system clock source
  *            @arg RCC_SYSCLKSource_LSI:    LSI selected as system clock source
  *            @arg RCC_SYSCLKSource_HSI64:  HSI64 selected as system clock source
  *            @arg RCC_SYSCLKSource_HSI16:  HSI16 selected as system clock source
  *            @arg RCC_SYSCLKSource_EXTCLK: EXTCLK selected as system clock source
  */
uint8_t RCC_GetSYSCLKSource(void)
{
    uint32_t tmp = 0;
    //choose clock source
    tmp = (RCC->CFGR4 & RCC_CFGR4_ESSS) >> 7;

    if (tmp == 0) //RCC_CFGR.SWS to set SYSCLK
    {
        return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)) >> 2;
    }
    else //RCC_CFGR4.ESWSto set SYSCLK
    {
        return ((uint8_t)((RCC->CFGR4 & RCC_CFGR4_ESWS)) >> 3 | 0x10);
    }
}

/**
  * @brief  Configures the AHB clock (HCLK).
  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
  *         the system clock (SYSCLK).
  *         This parameter can be one of the following values:
  *            @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
  *            @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
  *            @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
  *            @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
  *            @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
  *            @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
  * @retval None
  */
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{
    uint32_t tmpreg = 0;
    /* Check the parameters */
    assert_param(IS_RCC_HCLK(RCC_SYSCLK));
    tmpreg = RCC->CFGR;
    /* Clear HPRE[3:0] bits */
    tmpreg &= ~RCC_CFGR_HPRE;
    /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
    tmpreg |= RCC_SYSCLK;
    /* Store the new value */
    RCC->CFGR = tmpreg;
}

/**
  * @brief  Configures the APB clock (PCLK).
  * @param  RCC_HCLK: defines the APB clock divider. This clock is derived from
  *         the AHB clock (HCLK).
  *         This parameter can be one of the following values:
  *            @arg RCC_HCLK_Div1: APB clock = HCLK
  *            @arg RCC_HCLK_Div2: APB clock = HCLK/2
  *            @arg RCC_HCLK_Div4: APB clock = HCLK/4
  *            @arg RCC_HCLK_Div8: APB clock = HCLK/8
  *            @arg RCC_HCLK_Div16: APB clock = HCLK/16
  * @retval None
  */
void RCC_PCLKConfig(uint32_t RCC_HCLK)
{
    uint32_t tmpreg = 0;
    /* Check the parameters */
    assert_param(IS_RCC_PCLK(RCC_HCLK));
    tmpreg = RCC->CFGR;
    /* Clear PPRE[2:0] bits */
    tmpreg &= ~RCC_CFGR_PPRE;
    /* Set PPRE[2:0] bits according to RCC_HCLK value */
    tmpreg |= RCC_HCLK;
    /* Store the new value */
    RCC->CFGR = tmpreg;
}



/**
  * @brief  Configures the I2C1 clock (I2C1CLK).
  * @param  RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
  *         from the HSI or System clock.
  *         This parameter can be one of the following values:
  *            @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
  *            @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
  *            @arg RCC_I2C1CLK_PCLK: I2C1 clock = PCLK Clock
  * @retval None
  */
void RCC_I2C1CLKConfig(uint32_t RCC_I2CCLK)
{
    uint32_t tmpreg = 0, tmp = 0 ;
    /* Check the parameters */
    assert_param(IS_RCC_I2C1CLK(RCC_I2CCLK));
    /*Clear I2C1CLK_SEL bit*/
    RCC->CFGR4 &= ~RCC_CFGR4_I2C1CLK_SEL;
    tmp = RCC_I2CCLK >> 4;

    if (tmp == 0)
    {
        tmpreg = RCC->CFGR3;
        /*Clear I2C1SW bit*/
        tmpreg &= RCC_CFGR3_I2C1SW;
        /*Set I2C1SW bit according to RCC_I2CCLK*/
        tmpreg |= RCC_I2CCLK << RCC_CFGR3_I2C1SW_Pos;
        /*Store the new value*/
        RCC->CFGR3 = tmpreg ;
    }
    else
    {
        RCC->CFGR4 |= RCC_CFGR4_I2C1CLK_SEL;
    }
}

/**
  * @brief  Configures the I2C2 clock (I2C2CLK).
  * @param  RCC_I2CCLK: defines the I2C2 clock source. This clock is derived
  *         from the HSI or System clock.
  *         This parameter can be one of the following values:
  *            @arg RCC_I2C2CLK_HSI: I2C2 clock = HSI
  *            @arg RCC_I2C2CLK_SYSCLK: I2C2 clock = System Clock
  *            @arg RCC_I2C2CLK_PCLK: I2C2 clock = PCLK Clock
  * @retval None
  */
void RCC_I2C2CLKConfig(uint32_t RCC_I2CCLK)
{
    /* Check the parameters */
    assert_param(IS_RCC_I2C2CLK(RCC_I2CCLK));
    /* Clear I2CSW bit */
    RCC->CFGR4 &= ~RCC_CFGR4_I2C2CLK_SEL;
    /* Set I2CSW bits according to RCC_I2CCLK value */
    RCC->CFGR4 |= RCC_I2CCLK;
}

/**
  * @brief  Configures the UART1 clock (UART1CLK).
  * @param  RCC_UARTCLK: defines the UART clock source. This clock is derived
  *         from the HSI or System clock.
  *         This parameter can be one of the following values:
  *            @arg RCC_UARTCLK_PCLK: UART1 clock = APB Clock (PCLK)
  *            @arg RCC_UARTCLK_SYSCLK: UART1 clock = System Clock
  *            @arg RCC_UARTCLK_LSE: UART1 clock = LSE Clock
  *            @arg RCC_UARTCLK_HSI: UART1 clock = HSI Clock
  * @retval None
  */
void RCC_UART1CLKConfig(uint32_t RCC_UARTCLK)
{
    /* Check the parameters*/
    assert_param(IS_RCC_UARTCLK(RCC_UARTCLK));
    /* Clear UART1SW bit */
    RCC->CFGR3 &= ~RCC_CFGR3_UART1SW;
    /* Set UART1SW bits according to RCC_UARTCLK value */
    RCC->CFGR3 |= RCC_UARTCLK << RCC_CFGR3_UART1SW_Pos;
}

/**
  * @brief  Configures the UART2 clock (UART2CLK).
  * @param  RCC_UARTCLK: defines the UART clock source. This clock is derived
  *         from the HSI or System clock.
  *         This parameter can be one of the following values:
  *            @arg RCC_UARTCLK_PCLK: UART2 clock = APB Clock (PCLK)
  *            @arg RCC_UARTCLK_SYSCLK: UART2 clock = System Clock
  *            @arg RCC_UARTCLK_LSE: UART2 clock = LSEClock
  *            @arg RCC_UARTCLK_HSI: UART2 clock = HSI Clock
  * @retval None
  */
void RCC_UART2CLKConfig(uint32_t RCC_UARTCLK)
{
    /* Check the parameters*/
    assert_param(IS_RCC_UARTCLK(RCC_UARTCLK));
    /* Clear UART2SW bit */
    RCC->CFGR3 &= ~RCC_CFGR3_UART2SW;
    /* Set UART2SW bits according to RCC_UART2CLK value */
    RCC->CFGR3 |= RCC_UARTCLK << RCC_CFGR3_UART2SW_Pos;
}

/**
  * @brief  Configures the UART3 clock (UART3CLK).
  * @param  RCC_UARTCLK: defines the UART clock source. This clock is derived
  *         from the HSI or System clock.
  *         This parameter can be one of the following values:
  *            @arg RCC_UARTCLK_PCLK: UART3 clock = APB Clock (PCLK)
  *            @arg RCC_UARTCLK_SYSCLK: UART3 clock = System Clock
  *            @arg RCC_UARTCLK_LSE: UART3 clock = LSE Clock
  *            @arg RCC_UARTCLK_HSI: UART3 clock = HSI Clock
  * @retval None
  */
void RCC_UART3CLKConfig(uint32_t RCC_UARTCLK)
{
    /* Check the parameters*/
    assert_param(IS_RCC_UARTCLK(RCC_UARTCLK));
    /* Clear UART3SW[1:0] bits */
    RCC->CFGR3 &= ~RCC_CFGR3_UART3SW;
    /* Set UART3SW[1:0] bits according to RCC_UARTCLK value */
    RCC->CFGR3 |= RCC_UARTCLK << RCC_CFGR3_UART3SW_Pos;
}

/**
  * @brief  Returns the frequencies of the System, AHB and APB busses clocks.
  * @note   The frequency returned by this function is not the real frequency
  *         in the chip. It is calculated based on the predefined constant and
  *         the source selected by RCC_SYSCLKConfig():
  * @note   If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
  * @note   If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
  * @note   If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
  *         or HSI_VALUE(*) multiplied by the PLL factors.
  * @note   If SYSCLK source is HSI64, function returns constant HSI64_VALUE(***)
  * @note   (*) HSI_VALUE is a constant defined in hk32c030xx.h file (default value
  *         8 MHz) but the real value may vary depending on the variations
  *         in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
  * @note   (**) HSE_VALUE is a constant defined in hk32c030xx.h file (default value
  *         8 MHz), user has to ensure that HSE_VALUE is same as the real
  *         frequency of the crystal used. Otherwise, this function may
  *         return wrong result.
  * @note   The result of this function could be not correct when using fractional
  *         value for HSE crystal.
  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
  *         the clocks frequencies.
  * @note   This function can be used by the user application to compute the
  *         baudrate for the communication peripherals or configure other parameters.
  * @note   Each time SYSCLK, HCLK and/or PCLK clock changes, this function
  *         must be called to update the structure's field. Otherwise, any
  *         configuration based on this function will be incorrect.
  * @retval None
  */
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
    uint32_t tmp = 0, tmp1 = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0;
    uint32_t pllclk = 0 ;
    /* Get PLL clock source  --------*/
    pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

    if (pllsource == 0)
    {
        pllclk = HSI_VALUE >> 1;  //PLL source as HSI/2
    }
    else  //PLL source control by RCC_CFGR4.PPSS
    {
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
        pllsource = (RCC->CFGR4 & RCC_CFGR4_PPSS) >> RCC_CFGR4_PPSS_Pos;

        if (pllsource == 0x00)
        {
            /* HSE oscillator clock selected as PREDIV1 clock entry */
            pllclk = HSE_VALUE / prediv1factor;
        }
        else if (pllsource == 0x01)
        {
            /* HSI oscillator clock selected as PREDIV1 clock entry */
            pllclk = HSI_VALUE / prediv1factor;
        }
    }

    pllmull = ((RCC->CFGR & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos) + 2 ;
    pllclk = pllclk * pllmull;

    /* Get SYSCLK source -------------------------------------------------------*/
    if (((RCC->CFGR4 & RCC_CFGR4_ESSS) >> RCC_CFGR4_ESSS_Pos) != 0)
    {
        tmp = (RCC->CFGR4 & RCC_CFGR4_ESWS) >> RCC_CFGR4_ESWS_Pos;
        tmp = tmp | 0x10;
    }
    else
    {
        tmp = (RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos;
    }

    switch (tmp)
    {
        case 0x00:  /* HSI used as system clock */
            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
            break;

        case 0x01:  /* HSE used as system clock */
            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
            break;

        case 0x02:  /* PLL used as system clock */
            RCC_Clocks->SYSCLK_Frequency = pllclk;
            break;

        case 0x10:  /* LSE used as system clock */
            RCC_Clocks->SYSCLK_Frequency = LSE_VALUE;
            break;

        case 0x11:  /* LSI used as system clock */
            RCC_Clocks->SYSCLK_Frequency = LSI_VALUE;
            break;

        case 0x12:  /* HSI64 used as system clock */
            RCC_Clocks->SYSCLK_Frequency = HSI64_VALUE;
            break;

        case 0x13:  /* HSI16 used as system clock */
            RCC_Clocks->SYSCLK_Frequency = HSI16_VALUE;
            break;

        case 0x14:  /* EXTCLK_GPIOINPUT used as system clock */
            RCC_Clocks->SYSCLK_Frequency = EXTCLK_VALUE;
            break;

        default: /* HSI used as system clock */
            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
            break;
    }

    /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
    /* Get HCLK prescaler */
    tmp = RCC->CFGR & RCC_CFGR_HPRE;
    tmp = tmp >> RCC_CFGR_HPRE_Pos;
    presc = APBAHBPrescTable[tmp];
    /* HCLK clock frequency */
    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
    /* Get PCLK prescaler */
    tmp = RCC->CFGR & RCC_CFGR_PPRE;
    tmp = tmp >> RCC_CFGR_PPRE_Pos;
    presc = APBAHBPrescTable[tmp];
    /* PCLK clock frequency */
    RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
    /* Compute I2C1CLK clocks frequencies -----------------------------------*/
    /* I2C1CLK clock frequency */
    tmp1 = RCC->CFGR4 & RCC_CFGR4_I2C1CLK_SEL ;

    if (tmp1 == 0)
    {
        if ((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
        {
            /* I2C1 Clock is HSI Osc. */
            RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
        }
        else
        {
            /* I2C1 Clock is System Clock */
            RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
        }
    }
    else
    {
        /* I2C1 Clock is pclk Clock */
        RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
    }

    /* I2C2CLK clock frequency */
    if ((RCC->CFGR4 & RCC_CFGR4_I2C2CLK_SEL) == RCC_CFGR4_I2C2CLK_SEL_0)
    {
        /* I2C2 Clock is HSI Osc. */
        RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
    }
    else if ((RCC->CFGR4 & RCC_CFGR4_I2C2CLK_SEL) == RCC_CFGR4_I2C2CLK_SEL_1)
    {
        /* I2C2 Clock is System Clock */
        RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
    }
    else
    {
        /* I2C2 Clock is PCLK Clock */
        RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
    }

    if ((RCC->CFGR3 & RCC_CFGR3_UART1SW) == RCC_CFGR3_UART1SW_0)
    {
        /* UART1 Clock is System Clock */
        RCC_Clocks->UART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART1SW) == RCC_CFGR3_UART1SW_1)
    {
        /* UART1 Clock is LSE Osc. */
        RCC_Clocks->UART1CLK_Frequency = LSE_VALUE;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART1SW) == RCC_CFGR3_UART1SW)
    {
        /* UART1 Clock is HSI Osc. */
        RCC_Clocks->UART1CLK_Frequency = HSI_VALUE;
    }
    else
    {
        /* UART1 Clock is PCLK */
        RCC_Clocks->UART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
    }

    /* UART2CLK clock frequency */
    if ((RCC->CFGR3 & RCC_CFGR3_UART2SW) == RCC_CFGR3_UART2SW_0)
    {
        /* UART2 Clock is System Clock */
        RCC_Clocks->UART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART2SW) == RCC_CFGR3_UART2SW_1)
    {
        /* UART2 Clock is LSE Osc. */
        RCC_Clocks->UART2CLK_Frequency = LSE_VALUE;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART2SW) == RCC_CFGR3_UART2SW)
    {
        /* UART2 Clock is HSI Osc. */
        RCC_Clocks->UART2CLK_Frequency = HSI_VALUE;
    }
    else
    {
        /* UART2 Clock is PCLK */
        RCC_Clocks->UART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
    }

    /* UART3CLK clock frequency */
    if ((RCC->CFGR3 & RCC_CFGR3_UART3SW) == RCC_CFGR3_UART3SW_0)
    {
        /* UART3 Clock is System Clock */
        RCC_Clocks->UART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART3SW) == RCC_CFGR3_UART3SW_1)
    {
        /* UART3 Clock is LSE Osc. */
        RCC_Clocks->UART3CLK_Frequency = LSE_VALUE;
    }
    else if ((RCC->CFGR3 & RCC_CFGR3_UART3SW) == RCC_CFGR3_UART3SW)
    {
        /* UART3 Clock is HSI Osc. */
        RCC_Clocks->UART3CLK_Frequency = HSI_VALUE;
    }
    else
    {
        /* UART3 Clock is PCLK */
        RCC_Clocks->UART3CLK_Frequency = RCC_Clocks->PCLK_Frequency;
    }

    /* RTCCLK clock frequency */
    if ((RCC->BDCR & RCC_BDCR_RTC_SEL) == RCC_BDCR_RTC_SEL_0)
    {
        /* RTCCLK Clock is LSE Osc */
        RCC_Clocks->RTCCLK_Frequency = LSE_VALUE;
    }
    else if ((RCC->BDCR & RCC_BDCR_RTC_SEL) == RCC_BDCR_RTC_SEL_1)
    {
        /* RTCCLK Clock is LSI Osc. */
        RCC_Clocks->RTCCLK_Frequency = LSI_VALUE;
    }
    else if ((RCC->BDCR & RCC_BDCR_RTC_SEL) == RCC_BDCR_RTC_SEL)
    {
        /* RTCCLK Clock is HSE/32 Osc. */
        RCC_Clocks->RTCCLK_Frequency = HSE_VALUE / 32;
    }
    else
    {
        /* RTCCLK Clock is none */
    }
}

/**
  * @}
  */

/** @defgroup RCC_Group3 Peripheral clocks configuration functions
 *  @brief   Peripheral clocks configuration functions
 *
@verbatim
 ===============================================================================
             #####Peripheral clocks configuration functions #####
 ===============================================================================

    [..] This section provide functions allowing to configure the Peripheral clocks.
         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 (HSE
             divided by 32).
         (#) To reset the peripherals configuration (to the default state after device reset)
             you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
             RCC_APB1PeriphResetCmd() functions.

@endverbatim
  * @{
  */

/**
  * @brief  Configures the RTC clock (RTCCLK).
  * @note   As the RTC clock configuration bits are in the Backup domain and write
  *         access is denied to this domain after reset, you have to enable write
  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
  *         the RTC clock source (to be done once after reset).
  * @note   Once the RTC clock is configured it can't be changed unless the RTC
  *         is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
  *         This parameter can be one of the following values:
  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  *            @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
  * @note   The maximum input clock frequency for RTC is 2MHz (when using HSE as
  *         RTC clock source).
  * @retval None
  */
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
{
    /* Check the parameters */
    assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
    /* RTC clock source selection enable*/
    //RCC->BDCR |= RCC_BDCR_RTC_SEL_EN;
    /* Select the RTC clock source */
    RCC->BDCR |= RCC_RTCCLKSource;
}


/**
  * @brief  Enables or disables the RTC clock.
  * @note   This function must be used only after the RTC clock source was selected
  *         using the RCC_RTCCLKConfig function.
  * @param  NewState: new state of the RTC clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_RTCCLKCmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->BDCR |= RCC_BDCR_RTC_SEL_EN;
    }
    else
    {
        RCC->BDCR &= ~RCC_BDCR_RTC_SEL_EN;
    }
}


/**
  * @brief  Forces or releases the Backup domain reset.
  * @note   This function resets the RTC peripheral (including the backup registers)
  *         and the RTC clock source selection in RCC_BDCR register.
  * @param  NewState: new state of the Backup domain reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_BackupResetCmd(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->BDCR |= RCC_BDCR_BDRST;
    }
    else
    {
        RCC->BDCR &= ~RCC_BDCR_BDRST;
    }
}

/**
  * @brief  Enables or disables the AHB peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_AHBPeriph_GPIOA:   GPIOA clock
  *            @arg RCC_AHBPeriph_GPIOB:   GPIOB clock
  *            @arg RCC_AHBPeriph_GPIOC:   GPIOC clock
  *            @arg RCC_AHBPeriph_GPIOF:   GPIOF clock
  *            @arg RCC_AHBPeriph_CRC:     CRC clock
  *            @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
  *            @arg RCC_AHBPeriph_SRAM:    SRAM clock
  *            @arg RCC_AHBPeriph_DMA:    DMA clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->AHBENR |= RCC_AHBPeriph;
    }
    else
    {
        RCC->AHBENR &= ~RCC_AHBPeriph;
    }
}

/**
  * @brief  Enables or disables the AHB peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @param  RCC_AHB2Periph: specifies the AHB peripheral to gates its clock.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_AHB2Periph_DVSQ: DVSQEN clock
  * @param  NewState: new state of the specified peripheral reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->AHBENR2 |= RCC_AHB2Periph;
    }
    else
    {
        RCC->AHBENR2 &= ~RCC_AHB2Periph;
    }
}

/**
  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
  *            @arg RCC_APB2Periph_TEMPSEN: Tempersensor clock
  *            @arg RCC_APB2Periph_ADC:   ADC clock
  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
  *            @arg RCC_APB2Periph_UART1: UART1 clock
  *            @arg RCC_APB2Periph_TIM15:  TIM15 clock
  *            @arg RCC_APB2Periph_TIM16:  TIM16 clock
  *            @arg RCC_APB2Periph_TIM17:  TIM17 clock
  *            @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->APB2ENR |= RCC_APB2Periph;
    }
    else
    {
        RCC->APB2ENR &= ~RCC_APB2Periph;
    }
}

/**
  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
  * @note   After reset, the peripheral clock (used for registers read/write access)
  *         is disabled and the application software has to enable this clock before
  *         using it.
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_APB1Periph_TIM2:     TIM2 clock
  *            @arg RCC_APB1Periph_TIM3:     TIM3 clock
  *            @arg RCC_APB1Periph_TIM6:     TIM6 clock
  *            @arg RCC_APB1Periph_TIM14:    TIM14 clock
  *            @arg RCC_APB1Periph_WWDG:     WWDG clock
  *            @arg RCC_APB1Periph_SPI2:     SPI2 clock
  *            @arg RCC_APB1Periph_UART2:    UART2 clock
  *            @arg RCC_APB1Periph_UART3:    UART3 clock
  *            @arg RCC_APB1Periph_I2C1:     I2C1 clock
  *            @arg RCC_APB1Periph_I2C2:     I2C2 clock
  *            @arg RCC_APB1Periph_PWR:      PWR clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->APB1ENR |= RCC_APB1Periph;
    }
    else
    {
        RCC->APB1ENR &= ~RCC_APB1Periph;
    }
}

/**
  * @brief  Forces or releases AHB peripheral reset.
  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_AHBPeriph_GPIOA: GPIOA clock
  *            @arg RCC_AHBPeriph_GPIOB: GPIOB clock
  *            @arg RCC_AHBPeriph_GPIOC: GPIOC clock
  *            @arg RCC_AHBPeriph_GPIOF: GPIOF clock
  *            @arg RCC_AHBPeriph_CRC:   CRC clock
  *            @arg RCC_AHBPeriph_DMA:   DMA clock
  * @param  NewState: new state of the specified peripheral reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->AHBRSTR |= RCC_AHBPeriph;
    }
    else
    {
        RCC->AHBRSTR &= ~RCC_AHBPeriph;
    }
}


/**
  * @brief  Forces or releases AHB2 peripheral reset.
  * @param  RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_AHB2Periph_DVSQ: DVSQEN clock
  * @param  NewState: new state of the specified peripheral reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->AHBRSTR2 |= RCC_AHB2Periph;
    }
    else
    {
        RCC->AHBRSTR2 &= ~RCC_AHB2Periph;
    }
}

/**
  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock  and comp clock
  *            @arg RCC_APB2Periph_TEMPSEN: Tempersensor clock
  *            @arg RCC_APB2Periph_ADC:   ADC clock
  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
  *            @arg RCC_APB2Periph_UART1: UART1 clock
  *            @arg RCC_APB2Periph_TIM15:  TIM15 clock
  *            @arg RCC_APB2Periph_TIM16:  TIM16 clock
  *            @arg RCC_APB2Periph_TIM17:  TIM17 clock
  *            @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
  * @param  NewState: new state of the specified peripheral reset.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->APB2RSTR |= RCC_APB2Periph;
    }
    else
    {
        RCC->APB2RSTR &= ~RCC_APB2Periph;
    }
}

/**
  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
  *            @arg RCC_APB1Periph_UART2:  UART2 clock
  *            @arg RCC_APB1Periph_UART3:  UART3 clock
  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
  *            @arg RCC_APB1Periph_PWR:    PWR clock
  * @param  NewState: new state of the specified peripheral clock.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        RCC->APB1RSTR |= RCC_APB1Periph;
    }
    else
    {
        RCC->APB1RSTR &= ~RCC_APB1Periph;
    }
}

/**
  * @}
  */

/** @defgroup RCC_Group4 Interrupts and flags management functions
 *  @brief   Interrupts and flags management functions
 *
@verbatim
 ===============================================================================
             ##### Interrupts and flags management functions #####
 ===============================================================================
@endverbatim
  * @{
  */

/**
  * @brief  Enables or disables the specified RCC interrupts.
  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
  *         automatically generated. The NMI will be executed indefinitely, and
  *         since NMI has higher priority than any other IRQ (and main program)
  *         the application will be stacked in the NMI ISR unless the CSS interrupt
  *         pending bit is cleared.
  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
  *            @arg RCC_IT_PLLRDY: PLL ready interrupt
  *            @arg RCC_IT_HSI16RDY: HSI16 ready interrupt
  * @param  NewState: new state of the specified RCC interrupts.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_RCC_IT(RCC_IT));
    assert_param(IS_FUNCTIONAL_STATE(NewState));

    if (NewState != DISABLE)
    {
        /*Enable the selected interrupts */
        RCC->CIR |= (uint32_t)RCC_IT << 8;
    }
    else
    {
        /*Disable the selected interrupts */
        RCC->CIR &= ~((uint32_t)RCC_IT) << 8;
    }
}

/**
  * @brief  Checks whether the specified RCC flag is set or not.
  * @param  RCC_FLAG: specifies the flag to check.
  *         This parameter can be one of the following values:
  *         ** CR **
  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
  *            @arg RCC_FLAG_PLLRDY: PLL clock ready
  *                 ** BDCR **
  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
  *                 ** CSR **
  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
  *            @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
  *            @arg RCC_FLAG_PINRST: Pin reset
  *            @arg RCC_FLAG_V15PWRRST: V1.5 power domain reset
  *            @arg RCC_FLAG_PORRST: POR/PDR reset
  *            @arg RCC_FLAG_SFTRST: Software reset
  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset
  *            @arg RCC_FLAG_LPWRRST: Low Power reset
  *                 ** CR2 **
  *            @arg RCC_FLAG_HSI16RDY: HSI16 oscillator clock ready
  * @retval The new state of RCC_FLAG (SET or RESET).
  */
FlagStatus RCC_GetFlagStatus(uint32_t RCC_FLAG)
{
    uint32_t tmp = 0;
    uint32_t statusreg = 0;
    FlagStatus bitstatus = RESET;
    /* Check the parameters */
    assert_param(IS_RCC_FLAG(RCC_FLAG));
    /* Get the RCC register index */
    tmp = RCC_FLAG >> 5;

    if (tmp == 0)               /* The flag to check is in CR register */
    {
        statusreg = RCC->CR;
    }
    else if (tmp == 1)          /* The flag to check is in BDCR register */
    {
        statusreg = RCC->BDCR;
    }
    else if (tmp == 2)          /* The flag to check is in CSR register */
    {
        statusreg = RCC->CSR;
    }
    else                        /* The flag to check is in CR2 register */
    {
        statusreg = RCC->CR2;
    }

    /* Get the flag position */
    tmp = RCC_FLAG & FLAG_MASK;

    if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
    {
        bitstatus = SET;
    }
    else
    {
        bitstatus = RESET;
    }

    /* Return the flag status */
    return bitstatus;
}

/**
  * @brief  Clears the RCC reset flags.
  *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V15PWRRSTF,
  *         RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
  *         RCC_FLAG_LPWRRST.
  * @retval None
  */
void RCC_ClearFlag(void)
{
    /* Set RMVF bit to clear the reset flags */
    RCC->CSR |= RCC_CSR_RMVF;
}

/**
  * @brief  Checks whether the specified RCC interrupt has occurred or not.
  * @param  RCC_IT: specifies the RCC interrupt source to check.
  *         This parameter can be one of the following values:
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
  *            @arg RCC_IT_PLLRDY: PLL ready interrupt
  *            @arg RCC_IT_HSI16RDY: HSI16 ready interrupt
  *            @arg RCC_IT_CSSHSE  : HSE Clock Security System
  *            @arg RCC_IT_CSSLSE  : LSE Clock Security System
  * @retval The new state of RCC_IT (SET or RESET).
  */
ITStatus RCC_GetITStatus(uint32_t RCC_IT)
{
    ITStatus bitstatus = RESET;
    /* Check the parameters */
    assert_param(IS_RCC_GET_IT(RCC_IT));

    /* Check the status of the specified RCC interrupt */
    if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
    {
        bitstatus = SET;
    }
    else
    {
        bitstatus = RESET;
    }

    /* Return the RCC_IT status */
    return  bitstatus;
}

/**
  * @brief  Clears the RCC's interrupt pending bits.
  * @param  RCC_IT: specifies the interrupt pending bit to clear.
  *         This parameter can be any combination of the following values:
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
  *            @arg RCC_IT_PLLRDY: PLL ready interrupt
  *            @arg RCC_IT_HSI16RDY: HSI16 ready interrupt
  *            @arg RCC_IT_CSSHSE  : HSE Clock Security System
  * @retval None
  */
void RCC_ClearITPendingBit(uint32_t RCC_IT)
{
    /* Check the parameters */
    assert_param(IS_RCC_CLEAR_IT(RCC_IT));
    /* Clear the selected interrupt pending bits */
    RCC->CIR |= (uint32_t)RCC_IT << 16;
}


/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */


